System Architecture & Compute Model¶

1. 4-Stage Lifecycle Model¶

graph LR
    A["Stage 1: Ingress<br/>(Dimension Reduction & Normalization)"] --> B["Stage 2: Instructions<br/>(Declarative Specification)"]
    B --> C["Stage 3: Manager<br/>(Heterogeneous Coordination)"]
    C --> D["Stage 4: Output<br/>(Artifact Persistence)"]

Stage 1: Information Ingress¶

Dimensionality Reduction: Given feature matrix $X \in \mathbb{R}^{N \times d}$ and target register width $n$ where $d > n$, an orthogonal projection maps inputs to the leading components of variance: $$X_{\text{compressed}} = (X - \mu_X) W_n, \quad W_n \in \mathbb{R}^{d \times n}$$
Angle Normalization: Continuous components are scaled to the periodic domain of single-qubit rotations: $$\tilde{x}_j = 2\pi \left(\frac{x_j - x_{\min, j}}{x_{\max, j} - x_{\min, j}}\right) - \pi \in [-\pi, \pi]$$

Stage 2: Declarative Instructions¶

Decouples structural definition from runtime execution via serialized specifications:
Model Specification: Register width ($n$), layer repetition depth ($L$), ansatz topology, and differentiation scheme.
Optimization Specification: Learning rate ($\eta$), batch size ($B$), iteration limit, and loss formulation.

Stage 3: Heterogeneous Training Manager¶

Orchestrates data routing between compute tiers:
Classical pre-processing evaluates on high-throughput host hardware.
Intermediate parameters transfer to quantum simulation memory.
Quantum state evolves under parameterized unitary operations.
Expectation values return to host hardware for loss and decision boundary evaluation.
Backpropagation computes gradients through both classical and quantum operators.

Stage 4: Output Persistence¶

Standardized serialization of learned parameters, convergence metrics, and evaluation telemetry.